The present invention relates to flash memories and, more particularly, to a method of increasing the effective programming speed of a flash memory with no loss in reliability.
FIG. 1 illustrates the storage of a bit, either a zero bit or a one bit, in a cell of an electrically programmable memory (EPROM) such as a flash memory. For historical reasons, this process of storing data in a EPROM is called “programming” the EPROM. Specifically, the cell that is the subject of FIG. 1 is a single-level cell (SLC). Initially, the cell has a nominal threshold voltage V1 that represents a one bit. For example, after a block of a flash memory has been erased, all the cells have nominal threshold voltages V1. Because of unavoidable inaccuracies in the initializations of the cells, the actual threshold voltages are distributed around the nominal threshold voltage V1 according to a distribution curve 10. Then, to each cell that is to store a zero bit, a train of programming voltage pulses is applied, in order to inject electrons from the cell's silicon substrate through the cell's oxide layer into the cell's floating gate, until the cell's threshold voltage exceeds a reference voltage V0 that represents a zero bit. Because the electrons move through the oxide layer by quantum mechanical tunneling or by hot injection, because of non-uniformities in the cells' structures, and because the initial threshold voltages are distributed according to distribution curve 10, the threshold voltages of the cells that store zero bits are distributed above V0 according to a distribution curve 12.
A cell is read by comparing the cell's threshold voltage to a reference voltage VR that is above distribution curve 10 but below V0. If the cell's threshold voltage is below VR then the cell's contents are read as a one bit. If the cell's threshold voltage is at or above VR then the cell's contents are read as a zero bit.
Over time, the threshold voltages of the cells that store zero bits tend to drift downwards. Also shown in FIG. 1, in phantom, is a distribution curve 14 that represents the distribution of the threshold voltages of the cells that have been programmed to store zero bits after the passage of a considerable amount of time. V1, VR and V0 are selected to be sufficiently far apart to preserve the reliability of the flash memory despite this drift of the threshold voltages.
The voltage difference between the successive voltage pulses that are used to program a cell are relatively small, for two reasons. In the illustrated case of a SLC, and in the case of the highest voltage band of a multi-level cell (MLC, in which each of 2n voltage bands corresponds to one of the 2n possible patterns of n bits), too high a programming voltage imposes stress on the cell that reduces the cell's useful lifetime. In the case of the intermediate voltage bands of an MLC, distribution 12 must be sufficiently narrow to fit within the voltage band that represents the corresponding bit pattern. The use of small voltage increments implies that the programming of an array of flash cells is a relatively slow process. There is thus a widely recognized need for, and it would be highly advantageous to have, a method of programming flash memory cells that is faster than the presently known methods, with no loss in reliability.